INTRODUCTION
Wide band Sigma-Delta PLL modulator is based on PLL fractional N synthesis techniques along with Sigma-Delta modulation to randomize fractional N spurs. A modified Sigma-Delta function allows for suppression of Sigma-Delta noise at low frequencies & hence allows wider bandwidth. This is achieved using a fractional-N PLL architecture. They are capable of synthesizing frequencies at channel spacings less than the reference frequency. This helps to increase the reference frequency & hence reduces PLL’s locking time.
One of the major disadvantages of fractional-N PLL is the generation of high tones at multiples of channel spacings. Using digital Sigma-Delta modulation techniques in fractional-N PLL frequency synthesis eliminates this spurs. This is achieved by randomizing the feedback division ratio such that the quantization noise of the fractional-N PLL is transferred to high frequencies. Main advantages of this techniques are small frequency resolution, wide tuning bandwidth &fast switching speed. Low power & low area techniques are used in modified Sigma-Delta modulator. It has a total power consumption of 2mW & 1-GHz operation.
OVER VIEW
The proliferation of wireless products over past few years has been rapidly increasing. New wireless standards such as GPRS and HSCSD have brought new challenges to wireless transceiver design. One pivotal component of transceiver is frequency synthesizer.
Two major requirements in mobile applications are efficient utilization of frequency spectrum by narrowing the channel spacing and fast switching for high data rates. This can be achieved by using fractional- N PLL architecture. They are capable of synthesizing frequencies at channel spacings less than reference frequency. This will increase the reference frequency and also reduces the PLL’s lock time.
Fractional
CONVENTIONAL PLL
The advantages of this conventional S DPLL modulator is that they offer small frequency resolution, wider tuning bandwidth and fast switching speed. But they have insufficient bandwidth for current wireless standards such as GSM. so that they cannot be used as a closed loop modulator for digital enhanced codeless (DECT) standard. they efficiently filter out quantization noise and reference feed through for sufficiently small loop bandwidth.
WIDE BAND PLL
For wider loop band width applications bandwidth is increased. but this will results in residual spurs to occur. this due to the fact that the requirement of the quantization noise to be uniformly distributed is violated. since we are using S D techniques for frequency synthesis the I/P to the modulator is dc I/P which will results in producing tones even when higher order S D modulators are used. with single bit O/P level of quantization noise is less but with multi bit O/P s quantization noise increases. So the range of stability of modulator is reduced which will results in reduction of tuning range. More over the hardware complexity of the S D modulator is higher than Mash S D modulator. In this feed back feed forward S D modulator the loop band width was limited to nearly three orders of magnitudes less than the reference frequency. So if it is to be used as a closed loop modulator power dissipation will increase.
So in order to widen the loop band width the close-in-phase noise must be kept within tolerable levels and also the rise of the quantization noise must be limited to meet high frequency offset phase noise requirements. At low frequencies or dc the S D modulator transfer function has a zero which will results in addition of phase noise. For that the zero is moved away from dc to a frequency equal to some multiple of fractional division ratio. This will introduce a notch at that frequency which will reduce the total quantization noise. Now the quantization noise of modified S D modulator is 1.7 times and 4.25 times smaller than Mash S Dmodulator.
MODIFIED PLL
Advantages
1. Area of power dissipation was reduced.
2. Quantization noise was reduced.
3. Close-in-phase noise was reduced.
4. Can be used for closed loop applications.
5. Both low frequency and high frequency applications are possible.
6. Fast locking capability of the PLL.
7. High resolution (less than 10 Hz ).
Closed loop parameters.
Bandwidth = 200 KHz
Damping factor = 0.707
Change pump current = 50 micro Amp
VCO gain = 50MHz/V
Comparison with Mash S D PLL
Parameter proposed S D PLL Mash S D PLL
Area 0.71mm2 1mm2
Power 2mw 3mw
Capacitor size 152.56PF 17.58MF
Closed loop BW 200 KHz 30KHz
Close-in-phase noise 1.830 rms 7110 rms
Lock time 15MS 150MS
Features
The modified S DPLL modulator was implements on a 35mm CMOS technology. The chip includes S D modulator, frequency driver, phase frequency detector, charge pump and loop filter. An enternal VCO with frequency gain of 50MHz/r was assumed. Control signal for speed up was made enternal. Other pins include and bit frequency control hord and enable signal. Separate supply voltages were used for driver, charge pump and digital circuitry S D is mainly nominated by S D modulator and control interface.
In order to reduce power consumption supply voltage was reduced to 1.5 pipelining was used to compensate for loss in performance due to low supply voltage. So the power consumption was about 4.5 times reduced. The figure shows the power consumed by various components. The minimum lock time required for 100th resolution is less than 15MS. Less stand by power can be achieved since the time that the receiver must remain on channel scanning is reduced. The figure shows the locking characteristics of the PLL.
Motivation
Goal of this work
The goal of this work is to study the design feasibility of Sigma-Delta modulators, which should feature 12-14-bit resolution at 20-25Msample/s aimed for AD conversion in highperformancewireline or wireless communication applications, such as very high bit-ratedigital subscriber (VDSL), 3G, and even low-cost high-integration, high-flexibilitysoftware radio systems. The power consumption is limited to 150 mW--300 mW, in orderto obtain higher FOMs.
Problem statement
In analog-to-digital converters (ADCs), the requirements on sampling linearity, conversion rate, resolution, and power consumption are becoming tighter. As mentioned above,generally, in order to achieve a wide bandwidth and a high resolution, the sampling frequency, the noise-shaping order and the quantizer resolution should be increasedseparately or together.The process advance brings a thinner gate oxide and therefore a larger transconductance gm. As a result, the sampling speed (fs ) of a Sigma Delta ADC is continuously increasing.In early 1990’s the typical sampling frequency is tens of Mega-Hertz .Nowadays above hundred-Mega-Hertz switched-capacitor Sigma-Delta ADCs are implemented. Therefore, the bottleneck of speed increase is mainly the defective settling procedure of the integrators, since the large settling error results in non-linearity and the converter output will contain not only the increased noise floor but also the large harmonic distortions .
With respect to the high order noise-shaping, the cascade multi-bit Sigma-Delta modulator (MASH) structures by cascading the Sigma-Delta stages of the second or lower order are unconditionally stable. However, the circuit non-idealities, due to the mismatch in capacitor ratios and finite open-loop gains of the opamp, both result I an in complete cancellation of the quantization error of the former stages, which degrade
the dynamic range.An alternative is to use the single-loop high order structures, which have the advantage that they are insensitive to the capacitor mismatch and do not require high-performance analog circuits, but if the order of integrator is larger than 2, the modulator is prone to instability.
Therefore, the gain of the noise-transfer-function (NTF) has to be decreased by dividing the Lth-order polynomial D(Z), which results in a lower noise suppression of the base band quantization noise.Another problem associated with high-order singlestage modulators is the high coefficient spread leading to larger area, more power
consumption and poorer stability.
Solutions
In order to avoid a significant degradation of the SNR relative to the theoretical limit, the cascade multi-stage Sigma-Delta modulators based on the easily implemented stable first or second-order Sigma-Delta modulators are good choose. The key in this typ architecture is to design high-performance analog circuit’s building blocks that is difficult to be achieved in the modern CMOS technology.
The evolution of technology has been driven by the microprocessor industry, and hence does not always go in the best direction for the analog. However, the recent rapid growth of the wireless telecommunication device market has caused a boost in the development of advanced mixed signal technologies, such as silicon germanium-based BiCMOS, which is becoming a viable technology for the production of competitively priced and superior performance circuits.
Indeed, Sigma-Delta converters like any other data converters are inherently mixed signal circuits. The emergence of mixed-signal oriented SiGe-BiCMOS process now offers a more direct and effective alternative. The high transconductance of bipolar device for given current and area is higher than MOS transistors, therefore, it can be used to expand the open-loop gain and the unity-gain bandwidth of opamps, and the superior matching properties of bipolar devices make the offsets lower, which improves the common-mode rejection. Bipolar transistors also have considerably lower l/f noise than comparably-sized MOS transistors, which makes it possible to reduce system noise without devoting excessive area to MOS transistors forward in the signal path. In this scenario, this work primitively tried to adequately select, design, and develop high-performance key analog building blocks in BiCMOS for a multi-stage high-order Sigma-Delta modulator to meet our design goal.
The rapid development of modern deep-submicron CMOS processes and the ultimate goal being a single chip solution -- the system on a chip (SoC) -- bring the additional challenges in the data converter design, such as decreasing supply voltage, short channel effects in MOS devices, matching of devices, etc. Therefore, the requirements of sampling linearity,process matching, high DC gain and high gain-bandwidth product opamps in the traditional data converter architectures are becoming more and more difficult to be realized. This encourages me, in parallel, to concentrate on the development of novel high-order multibit Sigma-Delta ADC architectures.
The performance requirements of analog circuits should be significantly relaxed, so that the proposed Sigma-Delta ADC architectures are suitable for realizing high resolution broadband ADCs even as IC technologies advance. In this scenario, a novel low-disortion cascade and a low-disortion cascade multi-bit Sigma- Delta modulator with improved noise-transfer-function (NTF) are proposed in the mainstream CMOS process. Both architectures combine merits of low-distortion, cascaded Sigma-Delta structures and multi-bit quantization to achieve high dynamic range at low.
Future Work
Introduction
This work focused on studying high-speed high-resolution Sigma-Delta modulators for
communication systems. In this research area, techniques for relaxing the settling error
were the key. There were two general motives of this research: 1) the use of BiCMOS
processes in designing high DC-gain and bandwidth opamp to reduce settling errors in
Sigma-Delta modulators; 2) the use of developed architectures, which relaxing the
requirement on settling behavior of opamps. This chapter will summarize key research
contributions and results regarding the motives, and provide some recommendations for
future work.
Key research contributions
This research explored the implementation of high-speed, high-resolution, low-power
Sigma-Delta modulators in concert with diverse design techniques. According to the
knowledge of the author, key research contributions and results are summarized below:
• Analyzed and simulated impacts of circuit non-idealities in SC Sigma-Delta
modulators. Futhermore introduced a systematic method in design of SC Sigma-
Delta modulators.
• Demonstrated a wideband Sigma-Delta modulator with BiCMOS process at
reasonable power dissipation. An experimental prototype achieved 78.3dB (13bit)
of dynamic range and dissipated 140 mW by electrical simulation at 10 MS/s
Nyquist rate.
• Designed a new single-stage BiCMOS operational amplifier with one side gainboosting which has desirable properties for maximizing DC-gain and bandwidth.
• Provided a comprehensive analysis of the settling limitation in high-order Sigma-
Delta ADC architectures.
• Developed a new 2(mb)….1(mb) N-stage low distortion cascade Sigma-Delta
architecture at 8X oversampling ratio.
• Developed a new 3(mb)…1(mb) N-stage low distortion cascade Sigma-Delta
architecture with improved NTF at 8X oversampling ratio.
Conclusion
In this dissertation, the resolution and the speed limitation of the existing Sigma-Delta
ADC architectures have been discussed. A cascade BiCMOS Sigma-Delta modulator has been presented. In this design, the operational amplifier (opamp) with high dc gain and gain-bandwidth-product has been achieved by using the advanced BiCMOS technology. In order to meet with the main-stream sub-micron CMOS processes two low-distortion cascade Sigma-Delta ADC architectures have been proposed. The low
distortion cascade Sigma-Delta architecture minimizes the signal level at the integrators of the first stage by using a feed forward path from the input directly to the input of the
quantizer, therefore, STF=1. The advantages of this proposed architecture are relaxed
requirement on the opamp gain-bandwidth-product up to 2 fs, which is lower than 3-4 fS in other traditional Sigma-Delta modulator implementations, and reduced sensitivitiy to
nonidealities of circuits, such as finite dc-gain of opamps and capacitor mismatching.
Particularly the non-linearity of the opamps is also reduced. The low distortion cascade Sigma-Delta architecture achieves the same performance as the modulator. Additionally, the proposed approach realizes the modified FIR-NTF, by replacing two DC-zeros with a pair complex-conjugat zeros, to suppress the in-band noise floor at high-frequencies. Hence, these architectures are particularly suitable for realizing wide bandwidth ADCs as well as for low-power design as IC technologies advance.
Recommended future work
Demonstrations of the proposed modulators by using advanced CMOS processes would be a good next step in this area. In addition, the design of low-power programmable
decimation filters is another area where further research is demanded. High-linear DAC
will be a critical part, which should be further investigated, developed and implemented in the future.
CONCLUSION
A wide band PLL modulator for wireless applications is reported. This modulator is based on PLL fractional –N frequency synthesis techniques along with S D modulation to randomize fractional-N spurs. The modified S D function allows for suppression of S D noise at low frequencies and hence allows wider loop band width. Also S D quantization noise is reduced by using a truly differential logic implementation of fractional phase selection divide. The wide band width of 200KHz makes the proposed S D PLL suitable closed loop modulation.
REFERENCES
1. IEEE TRANSACTIONS ON CIRCUITS&SYSTEMS
FEB’03
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